The present invention relates to a semiconductor device and particularly to a technique applicable effectively to a semiconductor device which is assembled using a lead frame.
According to a known technique (see, for example, Patent Literature 1), there are used ground coupling portions arranged between a semiconductor chip and inner leads and coupled electrically by wire bonding to pads for ground of the semiconductor chip, the ground coupling portions being electrically coupled to and supported by tab suspending leads to stabilize the ground potential.
There also is known a technique which uses a lead frame having die pads smaller in size than a semiconductor chip and couples suspending leads of the lead frame and inner leads with each other using an insulating tape (see, for example, Patent Literature 2).
[Patent Literature 1]
Japanese Unexamined Patent Publication No. Hei 11 (1999)-168169
[Patent Literature 2]
Japanese Unexamined Patent Publication No. Hei 11 (1999)-224929